1. Field of the Invention
The present invention relates to the field of solid state electronics and more particularly to the field of solid state electronic logic circuits.
2. Description of the Prior Art
In designing logic circuits, attempts have been made to obtain the benefits of Gallium Arsenide (GaAs) technology while minimizing the disadvantages. In particular, GaAs provides considerably greater field effect transistor (FET) channel electron mobility than conventional semiconductors. Further, GaAs wafers exhibit very low parasitic capacitance. These factors allow fabrication of much faster transistors in GaAs than silicon.
Since GaAs depletion-mode metal-semiconductor FET (MESFET) technology has the longest manufacturing history of the GaAs technologies, the depletion-mode technology presently offers more promise for easy, cost-effective production of commercial GaAs logic circuits. In GaAs logic circuit applications, MESFET threshold voltages may range from +0.4 to -2.0 V and gate-source voltages may be as low as -3.0 V. As the gate-source supply voltage becomes more negative, power dissipation increases. As threshold voltages approach 0.0 V, less negative (lower power) gate-source supply voltages can be used, reducing power dissipation. Reduced power dissipation becomes important in designing GaAs logic gate arrays of appreciable size (e.g. larger than 80 gates). In depletion-mode GaAs FET logic gate array designs, where power dissipation may be several milliwatts per gate, the ability to use low power supply voltages is very important. However, since manufacturing tolerances become critical as threshold voltages approach 0.0 V, a common compromise for the nominal low voltage supply is -2 V. While this eases manufacturing tolerances, which are of critical concern to cost-effective commercial manufacture of logic gate arrays, the low nominal power supply voltage limits the nominal voltage swing of the output of the circuit. Although this reduced nominal output voltage swing increases the switching speed of the output of the circuit, it substantially reduces the noise margin of the next logic circuit. As a result, the reduced nominal output voltage swing increases the susceptibility of the next logic circuit to triggering in response to unwanted noise in the connecting lines.
Although depletion-mode FET manufacturing technology has the longest manufacturing history of the GaAs technologies, depletion-mode FETs made from present day GaAs technology still have relatively poor matching qualities, which increases the difficulty of designing cost-effective logic gate arrays using large numbers of gates. Device matching problems and process limitations are even greater problems in enhancement-mode FET circuit production. In particular, due to limitations in the production of both of these technologies, from device to device on a single logic gate array chip, the logic threshold voltage and output voltage may vary considerably. In a gate array, this is a substantial problem since any one input gate of a given logic circuit can be connected to an output gate of any other logic circuit. These variations in input logic threshold voltage and output voltage can decrease noise margins and interfere with the intended system operations.
Even when such depletion-mode and enhancement-mode circuits are designed to be insensitive to such variations in output voltage swing, under certain operating conditions the output voltage swing will be reduced due to forward biasing of an FET. In particular, the source resistance inherent in an output FET produces an undesired voltage drop in response to increased gate current resulting from forward biasing of the FET. This adds to the drain-to-source voltage drop across the FET, which reduces the output voltage swing when the FET is used in an inverter.
In co-pending Patent Application for FET Gate Current Limiter Circuits filed on Mar. 24, 1986, Ser. No. 843,166, in the name of David P. Laude and Glenn E. Noufer, assigned to the same assignee as the present Application, the circuits maintained a relatively large output voltage swing that provided relatively high insensitivity to unwanted noise at the logic inputs to the circuits that would otherwise have caused undesired changes in the output logic state. This large output swing was maintained under relatively adverse operating conditions in which an output FET was normally forward biased or in which it became forward biased at high temperatures, by limiting the forward biasing of the output FET in the circuit. Since the unwanted noise may be caused by capacitive coupling effects from long interconnect lines when the inputs of many of the circuits arranged in a gate array are connected in parallel, the advantages of these GaAs logic circuits were of special interest in the manufacture of large gate arrays.
Such prior FET Gate Current Limiter Circuits used the output FET to control the application of a logic signal from an input to an output. The output FET inherently had parasitic gate-to-source and gate-to-drain diodes. A control signal applied to the gate of the output FET controlled the application of the logic signal to the output through the output FET. Where such FET was an enhancement-mode GaAs device, the gate voltage could be of a value that tended to forward bias these diodes under all operating conditions and tended to significantly increase the gate current. A limiter circuit in series with the gate of the output FET was effective to limit the gate current and thus limit the forward biasing of the parasitic and circuit diodes. This reduced the effect on the gate current of variations in the power supplies to the output FET, process variations and operating temperature variations. Further, limiting the gate current limited the voltage drop resulting from the source resistance of the FET, maintaining the voltage swing of the logic signal at the output at desired levels. If the gate current were not limited, the resulting greater forward bias of those diodes would have caused an increase in the current drain from a voltage supply that biased the output FET. The unlimited forward bias would also have resulted in a greater voltage drop from drain-to-source across the output FET, reducing the voltage swing at the output and resulting in lower noise margin.
While such prior FET Gate Current Limiter Circuits provided the advantages noted above, it is also of interest to provide high speed switching of the gate voltage to the output FET that controls the application of a logic signal from the input to the output, while at steady state limiting the gate current to control the forward biasing of the gate-to-source and the gate-to-drain diodes of the output FET. Moreover, it is of interest to provide both of these advantages over a relatively wide range of process-induced and operating temperature-induced variations in the threshold voltages of the logic devices.
In the FET Gate Current Limiter Circuits of such co-pending Application, the power dissipated by the source resistance of the output FET was directly proportional to the gate current. Also, the switching speed of the gate of the output FET was dependent upon the rate of change of the gate voltage with time. Thus, the DC power requirements were for low gate current while the AC power requirements were for high gate current. Since the limiter circuit was effective to limit the gate current by using a control FET having a gate connected to its source, and the drain and source of the control FET were in series with the gate of the output FET, there was limited ability to provide the high AC current required for high speed switching and the low DC current required for minimizing power dissipation and maximizing the output voltage swing.